Prof. Ma. Jabbar
Dept of AI & ML, Vardhman College of Engineering, Vardhaman College of Engineering, Hyderabad, Telangana, India
Website: https://drakhiljabbar.in/
Member, IEEE Smart Cities Member, International Committee, IEEE Artificial Intelligence StandardsMember, Governing body, Internet Society India Hyderabad Chapter
Biography: Prof. Dr. MA.Jabbar is a Professor and Head of the Department AI&ML, Vardhaman College of Engineering, Hyderabad, Telangana, India. He obtained Doctor of Philosophy (Ph.D.) from JNTUH, Hyderabad, and Telangana, India. He has been teaching for more than 20 years. His research interests include Artificial Intelligence, Big Data Analytics, Bio-Informatics, Cyber Security, Machine Learning, Attack Graphs, and Intrusion Detection Systems.
Speech Title: The Science of Deepfakes: From Creation to Detection
Abstract: The fast development of Generative Artificial Intelligence has changed the way digital information is generated, enabling the creation of incredibly realistic synthetic images, videos and sounds, known as deepfakes. These technologies have major opportunities for entertainment, education, healthcare and digital media but also pose enormous difficulties around misinformation, identity theft, financial fraud, cybercrime and public trust. In this presentation, we take a holistic view of deepfakes from development to detection and where the technology has evolved over the past 5 years. It addresses the core concepts of deepfake creation such Generative Adversarial Networks (GANs), Autoencoders and Diffusion Models. The increasing societal influence is discussed with real-world cases from different countries. The discussion also discusses recent worldwide regulatory actions, including regulations established by including policies adopted by the European Union, the United States, India, and China, to promote transparency and responsible use of AI-generated media.
This Talk also covers current progress in deepfake detection using deep learning architectures such as CNNs, Transformers, attention-based models, multimodal learning, and cross-dataset generalization. This Talk also will also touch on the speaker’s academic contributions including novel deepfake detection frameworks such as Gabor-Xception, Enhanced Xception, WAF-X-Net and methods to evaluate robustness across datasets. The talk will conclude with future research directions such as multimodal forensics, provenance verification, real-time detection, explainable AI, and policy driven governance and emphasize that to effectively mitigate deepfake, an integrated approach is needed that combines technological innovations, regulatory frameworks, and raising public awareness to help build digital trust in the AI era.

Prof. Anand Nayyar
School of Computer Science，Duy Tan University, Da Nang,Vietnam
Website: https://scs.duytan.edu.vn/-khoa-khoa-hoc-may-tinh-tpb/55-nayyar-anand
Biography: Dr. Anand Nayyar received Ph.D (Computer Science) from Desh Bhagat University in 2017 in the area of Wireless Sensor Networks, Swarm Intelligence and Network Simulation. He is currently working in School of Computer Science-Duy Tan University, Da Nang, Vietnam as Professor, Scientist, Vice-Chairman (Research) and Director- IoT and Intelligent Systems Lab. A Certified Professional with 125+ Professional certifications from CISCO, Microsoft, Amazon, EC-Council, Oracle, Google, Beingcert, EXIN, GAQM, Cyberoam and many more. Published more than 200+ Research Papers in various High-Quality ISI-SCI/SCIE/SSCI Impact Factor- Q1, Q2, Q3, Q4 Journals cum Scopus/ESCI indexed Journals, 80+ Papers in International Conferences indexed with Springer, IEEE and ACM Digital Library, 60+ Book Chapters in various SCOPUS/WEB OF SCIENCE Indexed Books with Springer, CRC Press, Wiley, IET, Elsevier with Citations: (Google Scholar): 15700+, H-Index: 66 and I-Index: 254; (Scopus): 8300+; H-index: 48. Member of more than 60+ Associations as Senior and Life Member like: IEEE (Senior Member) and ACM (Senior Member). He has authored/co-authored cum Edited 60+ Books of Computer Science. Associated with more than 600+ International Conferences as Programme Committee/Chair/Advisory Board/Review Board member. He has completed 1 Grassroot and 1 ASEAN Project. He has 18 Australian Patents, 14 German Patents, 4 Japanese Patents, 41 Indian Design cum Utility Patents, 13 UK Patents, 1 USA Patent, 3 Indian Copyrights and 2 Canadian Copyrights to his credit in the area of Wireless Communications, Artificial Intelligence, Cloud Computing, IoT, Healthcare, Drones, Robotics and Image Processing. Awarded 50 Awards for Teaching and Research—Young Scientist, Best Scientist, Best Senior Scientist, Asia Top 50 Academicians and Researchers, Young Researcher Award, Outstanding Researcher Award, Excellence in Teaching, Best Senior Scientist Award, DTU Best Professor and Researcher Award- 2019, 2020-2021, 2022, 2022-2023 Distinguished Scientist Award by National University of Singapore, Obada Prize 2023, Lifetime Achievement Award 2023; Asian Admirable Achievers 2024; Distinguished Academic Leader 2024 and many more.
Speech Title: Securing the Next Generation of Intelligence: Threats, Attacks, and Defenses in Large Language Models
Abstract: Large Language Models (LLMs) are rapidly transforming enterprise systems, cybersecurity operations, education, research, customer support, and content generation. However, their growing adoption also introduces a new class of security, privacy, and trust challenges that traditional cyber defense mechanisms are not fully equipped to address. This keynote explores the evolving landscape of LLM security, focusing on critical threats such as prompt injection, jailbreak attacks, adversarial manipulation, training data poisoning, backdoor attacks, model inversion, sensitive information disclosure, insecure plugins, excessive agency, overreliance, and model theft. The talk will examine how attackers exploit the probabilistic and instruction-following nature of LLMs to generate harmful outputs, bypass safety controls, leak confidential information, or manipulate decision-making systems. Real-world scenarios across customer service, insurance claims, underwriting, and enterprise knowledge bases will highlight the practical impact of these risks. The keynote will also discuss the OWASP Top 10 for LLM applications, red teaming methodologies, black-box and white-box testing approaches, and emerging LLMSecOps practices. Finally, the session will present effective mitigation strategies, including prompt-layer firewalls, adversarial training, input validation, response monitoring, differential privacy, secure architecture, access control, and continuous model governance to build safer, trustworthy, and resilient AI systems.

Prof. Dr. Simon K.S. Cheung
Chief Information Officer, Hong Kong Metropolitan University,Hong Kong, China
Website: www.hkmu.edu.hk/kscheung
Biography: Dr. Simon K.S. Cheung obtained his BSc and PhD, both in Computer Science, from the City University of Hong Kong, and his Master of Public Administration with Distinction from the University of Hong Kong. He also received executive education from Oxford's Saïd Business School and Harvard's Kennedy School of Government. A Chartered Engineer as well as a Chartered Scientist by profession, he was admitted as a Chartered IT Professional Fellow of the British Computer Society, Fellow of the Institute of Mathematics and its Applications, Fellow of the Institution of Engineering and Technology, Fellow of the Hong Kong Institution of Engineers, and Fellow of the Hong Kong Computer Society.
Dr. Cheung is currently the Chief Information Officer of the Hong Kong Metropolitan University, overseeing the university IT services for teaching, learning, research and administration. He has been working in the higher education sector (with the Hong Kong Metropolitan University, the University of Hong Kong, the Hong Kong Baptist University, and the Chinese University of Hong Kong) for over 30 years in various administrative capacities, mainly in IT and educational technology, while also undertaking academic duties such as teaching, research, course development and programme accreditation. He has successfully implemented key projects pertaining to enterprise systems, process reengineering, campus infrastructure development, electronic library, blended learning, learning analytics and academic advising. He played a pivotal role in leading digital transformation for the Hong Kong Metropolitan University, deploying blended learning for SPACE, the University of Hong Kong, and implementing the Open Textbooks for Hong Kong project which found the first-ever open access textbook platform in Hong Kong.
Dr. Cheung is also active in research, with 200 publications in two distinct areas, namely, innovation and technology in education, and software and systems engineering. He has delivered 20 keynote and invited speeches for international conferences. Among other consultancy roles, he serves in the advisory board and editorial board for international journals, including the International Journal of Educational Technology in Higher Education (Springer), Australasian Journal of Educational Technology (ASCILITE), SN Computer Science (Springer) and Societal Impacts (Elsevier). Awards in recognition of his achievements include the Outstanding Research Publication Award from the Hong Kong Metropolitan University, Outstanding CIO Award from the Hong Kong IT Joint Council, and Honour for Excellence, CIO Award from the CIO Asia.
Speech Title: Analysis and Control of Use Cases with Shared Resources: A Formal Method based on Compositional Marked Graphs
Abstract:Use case driven system design is a software engineering approach where the whole system development lifecycle is dictated and driven by use cases. When there involve competition of shared resources among use cases (called conflicting use cases), erroneous situations such as deadlocks may occur. Therefore, analysis of these use cases for detection and avoidance of deadlocks has long been a difficult challenge, especially with a large volume of use cases. This keynote introduces a formal and theoretical sound method to identify conflicting use cases that would lead to deadlocks, based on compositional marked graphs. A subclass of Petri nets, marked graphs are used for modelling use cases where shared resources are represented by resource places. By composing them via their common resource places, the resulting augmented marked graph can be effectively analyzed in order to identify all potential deadlocks. Accordingly, control measures can be applied to avoid occurrence of these erroneous situations. Two versions of the Dining Philosophers problem are used for illustration.

Prof. Pascal Lorenz
University of Haute Alsace, France
Biography: Pascal Lorenz (lorenz@ieee.org) received his M.Sc. (1990) and Ph.D. (1994) from the University of Nancy, France. Between 1990 and 1995 he was a research engineer at WorldFIP Europe and at Alcatel-Alsthom. He is a professor at the University of Haute-Alsace, France, since 1995. His research interests include QoS, wireless networks and high-speed networks. He is the author/co-author of 3 books, 3 patents and 200 international publications in refereed journals and conferences. He was Technical Editor of the IEEE Communications Magazine Editorial Board (2000-2006), IEEE Networks Magazine since 2015, IEEE Transactions on Vehicular Technology since 2017, Chair of IEEE ComSoc France (2014-2020), Financial chair of IEEE France (2017-2022), Chair of Vertical Issues in Communication Systems Technical Committee Cluster (2008-2009), Chair of the Communications Systems Integration and Modeling Technical Committee (2003-2009), Chair of the Communications Software Technical Committee (2008-2010) and Chair of the Technical Committee on Information Infrastructure and Networking (2016-2017), Chair of IEEE/ComSoc Satellite and Space Communications Technical (2022-2023), IEEE R8 Finance Committee (2022-2023), IEEE R8 Conference Coordination Committee (2023). He has served as Co-Program Chair of IEEE WCNC'2012 and ICC'2004, Executive Vice-Chair of ICC'2017, TPC Vice Chair of Globecom'2018, Panel sessions co-chair for Globecom'16, tutorial chair of VTC'2013 Spring and WCNC'2010, track chair of PIMRC'2012 and WCNC'2014, symposium Co-Chair at Globecom 2007-2011, Globecom'2019, ICC 2008-2010, ICC'2014 and '2016. He has served as Co-Guest Editor for special issues of IEEE Communications Magazine, Networks Magazine, Wireless Communications Magazine, Telecommunications Systems and LNCS. He is associate Editor for International Journal of Communication Systems (IJCS-Wiley), Journal on Security and Communication Networks (SCN-Wiley) and International Journal of Business Data Communications and Networking, Journal of Network and Computer Applications (JNCA-Elsevier). He is senior member of the IEEE, IARIA fellow and member of many international program committees. He has organized many conferences, chaired several technical sessions and gave tutorials at major international conferences. He was IEEE ComSoc Distinguished Lecturer Tour during 2013-2014.
Speech Title: Architectures of Next Generation Wireless Networks
Abstract:Internet Quality of Service (QoS) mechanisms are expected to enable wide spread use of real time services. New standards and new communication architectures allowing guaranteed QoS services are now developed. We will cover the issues of QoS provisioning in heterogeneous networks, Internet access over 5G networks and discusses most emerging technologies in the area of networks and telecommunications such as IoT, SDN, Edge Computing and MEC networking. We will also present routing, security, baseline architectures of the inter-networking protocols and end-to-end traffic management issues.

Prof. Tao Yu
China Academy of Management Science, China
Website: https://www.researchgate.net/profile/Tao_Yu89
Biography: Professor Tao YU is a renowned domestic research expert in radio positioning technology and an industry leader. He is one of the top 100 pioneers of scientific and technological innovation in the new era in China in 2023. So far, he has published more than 200 papers, published two academic monographs, and applied for more than twenty invention patents. The two monographs are: (1) In 2017, the academic monograph "Technology of Passive Detection Location" funded by the national key publishing fund was published by the National Defense Industry Press. (2) In 2022, the English monograph "Passive Location Method Based on Phase Difference Measurement" was published by Bentham Press. In addition, three English monographs (co-authored) have been published so far.
Speech Title: PhyLock: A Dual-Domain Encrypted Continuous-Wave Phase Ranging Architecture for Physical-Layer-Secure Near-Field Authentication
Abstract:Proximity-based authentication systems—encompassing automotive digital keys, smart door locks, and contactless payment terminals—demand both high-precision distance measurement and robust resistance to relay attacks. Existing solutions often face a dilemma: they either lack physical-layer security mechanisms (e.g., BLE RSSI) or rely on expensive, deployment-constrained dedicated hardware (e.g., UWB), hindering large-scale adoption.
This paper presents PhyLock, a Dual-Domain Encrypted Continuous-Wave Phase Ranging (DE-CWPR) method that establishes a fundamentally new paradigm: "encryption as ranging." Unlike conventional approaches that treat ranging and security as independent layers, PhyLock™ deeply embeds cryptographic mechanisms into the physical-layer waveform itself.
The architecture operates across two coordinated dimensions. In the frequency domain, a coarse-to-fine strategy first obtains an initial distance estimate using fixed frequency differences, then constrains a dynamic frequency difference interval for refined measurement. A cryptographically seeded pseudorandom generator produces session-unique frequency differences, rendering the ranging signal unpredictable to unauthorized receivers. In the phase domain, random phase offsets—derived from the same pseudorandom sequence—are deliberately introduced to obfuscate phase observations while preserving the phase difference invariance required for distance computation.
A four-phase closed-loop protocol (secure wake-up, session key negotiation, encrypted ranging, and verification) ensures long-term security through periodic key refresh. The entire architecture is designed for low-cost commodity hardware, requiring only standard radio frequency integrated circuits with frequency synthesis and phase detection capabilities.
PhyLock achieves sub-centimeter ranging accuracy (±3 mm in near-field static scenarios) while providing cryptographic-grade protection against relay attacks, signal interception, and statistical analysis. This work offers a practical physical-layer security solution for next-generation near-field authentication applications.

Prof. Lu Leng
School of Software, Nanchang Hangkong University, China
Website: https://baike.baidu.com/item/%E5%86%B7%E7%92%90/3747234?fr=aladdin
Biography: LU LENG received his Ph.D degree from Southwest Jiaotong University, Chengdu, P. R. China, in 2012. He performed his postdoctoral research at Yonsei University, Seoul, South Korea, and Nanjing University of Aeronautics and Astronautics, Nanjing, P. R. China. He was a visiting scholar at West Virginia University, USA, and Yonsei University, South Korea. Currently, he is a full professor, doctoral supervisor, the dean of Institute of Computer Vision at Nanchang Hangkong University.
Prof. Leng has published more than 150 international journal and conference papers, including more than 80 SCI papers and three highly cited papers. He has been granted several scholarships and funding projects, including six projects supported by National Natural Science Foundation of China (NSFC). He serves as a reviewer of more than 100 international journals and conferences. His research interests include computer vision, biometric template protection, biometric recognition, medical image processing, data hiding, etc.
Prof. Leng was selected as one of the "World's Top 2% Scientists" four times, and awarded Jiangxi Youth May-4th Medal. He is an outstanding representative of "Innovation Talent" of Jiangxi Enterprise in "Science and Technology China", "Jiangxi Hundred-Thousand-Ten-thousand Talent Project", and "Jiangxi Voyage Project".
Speech Title: Advanced Information Aggregation
Abstract:Information Aggregation is the process of combining data or information from multiple dispersed sources into a single high-value output, which aims at optimizing decision-making, reducing redundancy, and improving system efficiency. This speech will introduce some advanced information aggregation technologies that can eliminate single-source bias, enhance the robustness and representativeness of results, and reduce data volume to ease subsequent analytical burdens, thereby providing strong support for accurate judgments in complex scenarios.

Prof. Wen-Cheng Lai
Ming Chi University of Technology, Taiwan
Biography: Wen-Cheng Lai (Senior Member, IEEE) is currently an Assistant Professor with the Department of Electrical Engineering, Ming Chi University of Technology, New Taipei City, Taiwan. He has been involved in the RF, Analog IC Integrated Design, Computer and Communications and Artificial Intelligence. He joined USS, Compal Electronics, Inc., Micro Star Intl Co., Ltd, and Quanta Computer Inc laptop PC design as a senior engineer from 1998 to 2006, respectively, and he worked with Hon Hai (Foxconn) Precision Industry Co., Ltd as smart phone senior design engineer from 2006 to 2007. From 2008 to 2013, he was a Manager of Core Technology Division with Toshiba Corp., From 2014 to 2017, he served in Director with AsusTek Computer Inc, and China Radio Association. And he was an Assistant Professor with the Dept of Electrical Engineering, National Penghu University of Science and Technology from 2018 to 2020. He was an Assistant Professor with the Dept of Electronic Engineering, National Yunlin University of Science and Technology from 2020 to 2023. He received the World Ranking Top 2% Scientists (2020~ until now) from Stanford University and Scopus Database.
Speech Title: Evaluation of Delayed Offloading and Throughput in Mobile Cloudlet
Abstract:Mobile edge is strongly influenced by its battery life contemporary it holds tiny embedded capacity and energy dissipation. also leads to an issue. Since surge count in the usage of mobile computing and cloud technology introduced with titled Mobile Cloud Computing (MCC). The offloading and throughput are emerged in MCC to attain low latency completion of computations along with considerable extent endorse of remote servers. The performance of such task is degraded due to delayed offloading in completion of task. This proposed threshold based multilevel offloading algorithm scheme and throughput were used for accelerating to offloading procedure simultaneously experiment network traffic and power dissipation. of embedded mobile and alignment concept simulated using python programming. This article presents throughput analysis for mobile cloudlet.

Selva Lakshman Murali
Senior Engineer, Samsung Austin Semiconductor, Austin, Texas, United States
Biography: Accomplished Research Engineer specializing in cutting-edge semiconductor circuit and physical design, with an established track record of innovation at industry-defining leaders, including Samsung and AMD. Demonstrated expertise in driving next-generation hardware advancements, focusing heavily on Power, Performance, and Area (PPA) optimizations for complex integrated circuits and advanced process nodes.
Combines deep foundational research with commercial silicon engineering to solve critical bottlenecks in VLSI design, physical implementation, and architectural efficiency. Recognized as a thought leader and inventor in the solid-state and electronic design automation (EDA) fields, holding two patents for novel circuit design methodologies. A frequent contributor to the broader research community, with approximately 90 Google Scholar citations reflecting the enduring impact of his work on modern chip design and PPA enhancement strategies.
Adept at bridging the gap between theoretical experimentation and high-volume manufacturing requirements. Passionate about leading technical investigations, streamlining physical design flows, and advancing semiconductor optimization to power high-performance computing, mobile, and next-generation compute architectures.
Speech Title: Autonomous Physical Design: A Survey of Machine Learning Algorithms, Formulations, and Measured PPA Outcomes Across the RTL-to-GDS Stack
Abstract:The scaling of CMOS technology to sub-3nm process nodes has exposed a fundamental limitation in conventional electronic design automation (EDA): the combinatorial optimization search space for full-chip physical design grows super-exponentially with transistor count, rendering heuristic-driven flows computationally intractable and structurally incapable of jointly optimizing power, performance, and area (PPA) across the design hierarchy. This work presents a systematic survey of machine learning (ML) methodologies being deployed across the RTL-to-GDS flow, with emphasis on algorithmic formulations, Markov Decision Process (MDP) constructions, and empirically validated PPA outcomes.
We characterize six algorithmic families — reinforcement learning (PPO/SAC), graph neural networks (GNN), Bayesian optimization, Transformer-based large language models, physics-informed surrogate models, and generative AI — and map each to its corresponding design stage, reward signal formulation, and measured impact. Key results drawn from peer-reviewed literature and publicly disclosed industry deployments include: 97% post-route timing prediction accuracy at synthesis using GNNs (IEEE TCAD 2023), 10× quality-of-results convergence improvement via RL-guided synthesis recipe exploration (DAC 2023), sub-4% error on full-chip IR drop and thermal estimation using ML surrogates replacing SPICE (ICCAD 2023), and a cumulative 24%/28%/43% improvement in area, power, and worst negative slack respectively across a fully ML-augmented design flow.
Production deployments at Google (TPUv5), NVIDIA (Blackwell), AMD (Zen 5 at TSMC N4P), and TSMC (N2/N3 cuLitho) corroborate these findings at scale. Collectively, the evidence indicates a structural transition from human-directed to algorithm-directed physical design, with full RTL-to-GDS autonomy credibly projected by 2030.

Saurabh Kakkar
Director / Program Manager – Credit AI Analytics & Reg. Compliance, Santander Bank, Dallas, Texas, United States
Biography: Saurabh Kakkar is a technology, artificial intelligence, data, and risk transformation leader with more than 15 years of experience delivering enterprise-scale programs across global financial institutions, including Santander Bank, Credit Suisse, PwC, Citco Fund Services, and Ernst & Young.
He currently serves as Director / Program Manager for the Basel Data Repository at Santander Bank, where he leads strategic initiatives involving regulatory data management, enterprise analytics, artificial intelligence, automation, and Basel III and CRR compliance. His work focuses on applying Generative AI, Large Language Models, Retrieval-Augmented Generation, Explainable AI, and advanced data engineering to improve regulatory interpretation, reporting accuracy, governance, and operational efficiency.
His professional and research interests include trustworthy AI, Explainable AI, responsible machine learning, AI governance, financial technology, regulatory technology, intelligent decision-support systems, predictive analytics, and enterprise digital transformation. He is also actively engaged in academic and professional activities as an author, researcher, peer reviewer, conference speaker, and evaluator of emerging research in artificial intelligence and computer science. His work aims to bridge the gap between academic innovation and practical, auditable, and responsible enterprise implementation.
Speech Title: Trustworthy Generative AI for Regulated Enterprise Systems: Explainability, Governance, and Data Engineering from Financial Risk to Computer Science Practice
Abstract:Generative Artificial Intelligence and Large Language Models are rapidly transforming enterprise decision-making, regulatory analysis, data management, and knowledge-intensive business processes. However, their adoption within regulated and high-impact environments introduces significant challenges related to explainability, accuracy, governance, data quality, model risk, privacy, bias, traceability, and supervisory auditability.
This invited talk presents a practical and research-oriented framework for designing trustworthy Generative AI systems for regulated enterprises. The presentation examines how Large Language Models, Retrieval-Augmented Generation, Explainable AI, and enterprise data engineering can be combined to create intelligent systems that are not only effective, but also transparent, controlled, traceable, and suitable for critical decision-making.
The talk will discuss key architectural components, including governed data pipelines, authoritative knowledge retrieval, prompt and model controls, human-in-the-loop validation, explainability mechanisms, risk-based testing, performance monitoring, and audit evidence. It will also highlight practical use cases in regulatory interpretation, financial risk management, compliance automation, enterprise reporting, and intelligent decision support.
Particular attention will be given to the gap between experimental AI prototypes and production-ready enterprise systems. The presentation will outline common implementation failures and propose a lifecycle approach covering design, validation, deployment, governance, monitoring, and continuous improvement.

Ishan Kumar
Senior Verification Engineer , Nvidia, Santa Clara,USA
Biography: Ishan is a Design Verification AI Engineer at NVIDIA, where he works on developing and validating next-generation GPU and AI hardware technologies. He earned his Bachelor's degree in Electronics and Communication Engineering from BITS Pilani, India, and later completed his Master's degree in Computer Engineering from Texas A&M University, USA.
At NVIDIA, Ishan focuses on ensuring the reliability and correctness of complex hardware designs through advanced verification methodologies and AI-driven automation. His work includes developing UVM/SystemVerilog-based verification environments, creating AI-assisted verification workflows, automating regression analysis, implementing functional coverage strategies, debugging RTL designs, and leveraging Python and machine learning techniques to improve verification efficiency. His interests lie at the intersection of hardware design, artificial intelligence, and automation, with a passion for building scalable solutions that enhance engineering productivity.
Outside of work, Ishan enjoys playing chess and tennis. Chess strengthens his analytical thinking and strategic problem-solving skills, while tennis helps him stay active and maintain a healthy work-life balance. He is passionate about continuous learning, emerging technologies, and applying AI to solve challenging engineering problems.
Speech Title: AI-Driven Design Verification: Transforming the Future of Chip Development
Abstract:As modern semiconductor designs continue to grow in complexity, traditional design verification methodologies face increasing challenges in achieving comprehensive coverage while meeting aggressive product development timelines. At the same time, the rapid advancement of artificial intelligence (AI) is creating new opportunities to transform how verification is performed, making it more intelligent, automated, and efficient.
This talk explores how AI is reshaping the design verification landscape for next-generation chip development. Beginning with an overview of the chip design and verification lifecycle, the session highlights the critical role verification plays in ensuring the correctness, reliability, and performance of today's complex GPU and AI accelerator architectures. It then examines how AI techniques can be integrated into verification workflows to improve productivity, reduce manual effort, and accelerate bug discovery.
The discussion will cover practical applications of AI in design verification, including intelligent test generation, regression analysis, coverage optimization, failure triage, debug assistance, and automated root-cause analysis. The talk will also discuss how data-driven approaches and large language models are enabling engineers to automate repetitive tasks, analyze vast amounts of verification data, and make more informed decisions throughout the development cycle.
Beyond current applications, the session will provide insights into emerging trends, challenges, and opportunities at the intersection of AI and hardware engineering. It will conclude with perspectives on the future of AI-assisted verification and the evolving skill set expected of engineers entering the semiconductor industry. Attendees will gain an understanding of how AI is transforming chip development and how these innovations are shaping the next generation of hardware design and verification.